1. Field of the Invention
The present invention relates to a phase adjustment apparatus of a transmission signal transmitted between apparatuses while synchronized with a clock and a semiconductor test apparatus using the phase adjustment apparatus. More particularly, the present invention relates to a phase adjustment apparatus and a semiconductor test apparatus for automatically correcting irregularities of propagation delay of a transmission signal transmitted between apparatuses while synchronized with a high-speed clock, so that the transmission signal can be received at stable and optimal timing in a receiving end.
2. Related Art
FIG. 6 shows the representative schematic configuration of a semiconductor test apparatus. The main configuration elements include a timing generator TG, a pattern generator PG, a waveform formatter FC, a pin electronics PE, a logic comparator DC, and a fail memory FM. Here, since the semiconductor test apparatus is publicly known and it is technically well known, each configuration element will not be described in detail.
In the mean time, as the signals transmitted between those elements while being synchronized with a clock, there are thousands of pieces of pattern data PAT, hundreds of expected values EXP, a fail signal FD, an address signal AD, etc., and the units are coupled to each other with cables of few meters which is relatively long. In addition, the signals are mainly transmitted in the form of a differential transmission signal. And with regard to the inside of each unit, there are lots of circuit parts where signals are transmitted between the circuits or LSIs with a high-speed clock. With regard to all of those signals, although there are temperature change, time lapse, board replacement, etc., it is necessary for the signals to be stably transmitted between the apparatuses or circuits while synchronized with a clock.
FIG. 1 shows a configuration example of a conventional phase adjustment apparatus of a transmission signal for performing a phase adjustment of timing for a clock. Further, although the transmission signals in the semiconductor test apparatus may exist in large numbers and the clocks may be applied at different timing, it is herein simply assumed that one transmission signal is received and retiming is performed on the signal with a clock.
These main configuration elements includes a first clock CLK1, a second clock CLK2, a first apparatus 100, a connection line 300, a delay device 80, and a second apparatus 200.
The first and second clocks CLK1 and CLK2 are high-speed clocks of a same period, e.g. clocks of 500 MHz (2 nano seconds in period), where there is an undetermined phase difference of a few hundreds pico seconds, which is to be inputted in a timing state regulated to some degree, between the phases at the input terminals of both apparatuses. Further, the first and second clocks CLK1 and CLK2 are common clocks which are supplied to other circuits, a transmission unit or a reception unit, and the phase adjustment apparatus generally includes a clock buffer circuit (not shown) for distributing the clocks.
The first and second apparatuses 100 and 200 may be individual boards or units, or may be an LSI inside a same board. Particularly, it is herein assumed that they are LSIs built in a same board.
The first apparatus 100 includes an internal circuit 10 and a transmission unit 110 therein. The transmission unit 110 includes a flip-flop 20 as an example of principle configuration. A transmission signal 20s which results from performing retiming of an input signal 10s of the input terminal of the flip-flop 20 with the first clock CLK1 is outputted, passed through the connection line 300 and the delay device 80, and supplied to the second apparatus 200.
The connection line 300 is a pattern wiring between both the LSIs. The amount of the propagation delay caused by a pattern is different due to the conductivity of the material of a board, the thickness of a multi-layer board, as well as the inner layer and surface layer of a multi-layer board, e.g. is 1 nano-second more or less for 10 cm.
It is practically difficult to match all of the lengths of the pattern wirings of thousands of transmission signals which connect both the LSIs or the amounts of the propagation delay. For example, if the lengths of the pattern wirings are different by 1 cm, the difference between the amounts of the propagation delay becomes 0.1 nano second more or less. Further, although the lengths of the lines are the same, the amounts also vary due to the difference of the wiring patterns across the inner or surface layer of the multi-layer board actually manufactured or the difference of the number of via holes crossing. And there is also jitter or waveform distortion caused by the reflection of the transmission signal.
The delay device 80 is semi-fixed delay means. In other words, a fixed delay device of a desired delay amount is optionally mounted, whereby it outputs the delay signal 80s which has been delayed to some extent from the transmission signal 20s received. Therefore, the reception unit 210 of the second apparatus 200 can perform retiming of the transmission signal 20s with the second clock CLK2 under a timing condition whose set-up time or hold time is stable.
The reception unit 210 of the second apparatus 200 includes a flip-flop 82 which receives the delay signal 80s and supplies the retiming signal 82s on which retiming has been performed with the second clock CLK2 to the internal circuit 90.
According to the above conventional configuration, for the stable retiming condition, it is necessary to finally attach the delay device 80 whose delay amount is 0.1 to 1.0 nano second more or less after performing replacing adjustment. In addition, there is a difficulty that it takes time for adjustment work to adjust the fixed delay device of a desired delay amount while selecting it. And there is also a difficulty that in response to tens or hundreds of transmission signals, an area is needed to mount a lot of the delay devices 80 on a board, so the mounting density of the board decreases.
And if the delay characteristics of the transmission unit 110 or the reception unit 210 of a built-in LSI changes, or the clock timing of the first or second clock CLK1 or CLK2 is changed in design, the delay amount of the delay device 80 previously obtained cannot be applied, and it needs to be adjusted again.
According to board replacement or cable replacement, it is necessary to care about the clock timing of the first or second clock CLK1 or CLK2 not to change. If it changes, there is a problem that the retiming operation in accordance with this becomes unstable.
In the above conventional art, it is necessary to adjust the delay amount of the delay device 80 and attach it for each transmission signal 20s. In addition, if the timing condition under which retiming is performed on the transmission signal 20s changes due to the board replacement, there might occur some of lots of transmission signals which are not necessarily in the stable timing state. And there is also manufacture irregularity in an IC or LSI itself or irregularity of propagation delay according to the difference of makers, whereby the timing does not always be in the optimal retiming state. And jitter or waveform distortion caused by reflection of the transmission signal also exits. According to this, if a high-speed clock whose operation margin is narrow is applied, there is a possibility that a malfunction is occasionally caused unless the optimal phase condition is set.
And since the propagation delay amount of a semiconductor IC is dependent upon temperature, a change in the propagation delay amount of the transmission unit, the reception unit, or a clock distribution circuit occurs, so the retiming condition might deviate from the stable state.
And in case of changing the period of a clock, the phase relation between the transmission signal received and the clock of the receiving end in which retiming is performed on the signal does not be in the optimal phase condition.
And as the power supply voltage condition or the surrounding temperature changes or time lapses, the retiming condition gets gradually out of the stable state.
In operation with the power source being supplied, it is often uncertain whether the apparatus is operating while maintaining the retiming state which was stable under the present power supply voltage condition and the surrounding temperature condition or not.
In terms of that point, the conventional art has a practical problem which is not desirable.